The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a plurality of one-transistor type memory cells.
One-transistor type memory cell consisting of one insulated gate field effect transistor (hereinafter abbreviated as IGFET) and one capacitor has been widely used in a dynamic random access memory device such as 256K bits devices or 1 M bits devices under development. To realize a high integration, various attempts have been conducted in the memory cells. For example, a memory cell in which the IGFET is formed on a major surface of the semiconductor substrate by a conventional manner and the capacitor is formed in a trench provided in the substrate was proposed by H. Sunami, et al. in an article "A CORRUGATED CAPACITOR CELL (CCC) FOR MEGABIT MOS MEMORIES", International Electron Devices Meeting, Dec. 15, 1982, Session 26. The proposed memory cell contributes to a high integration to some extent because the capacitor per se is formed in the trench. However, reduction in size of the IGFET is impossible because it is formed on the major surface of the substrate. Namely, the channel length must be 1.0 .mu.m or more to avoid a short channel effect, and each of source and drain regions formed on the major surface of the substrate must have a length of at least 3 .mu.m for forming contact portion at its upper surface. Further, the distance between a trench of one memory cell and a trench of an adjacent memory cell cannot be made small for preventing punch-through phenomenon of depletion layers which are spread from trenches of capacitor elements. In the surface portion, the punch-through can be prevented by a channel stopper region formed under a field insulating layer. However, from the deeper portion of the trench, the depletion layer of the capacitor element extends freely into the substrate. Therefore, in the prior art, if the depth of the trench becomes deeper to obtain a large capacitance in the memory cell, the distance must be made larger. Thus, the prior art has a limitation in providing a highly integrated memory device.